Austin, TX – February 4, 2017
Held in conjunction with the International Symposium on Code Generation and Optimization (CGO) 2017
Web site: https://dcahpo.wordpress.com/
8:30 Paper Session
8:30 : Workshop Introduction
8:35 : “Just-in-Time Compilation to FPGAs: User-Transparent Translation of
Machine Instructions to Hardware” Leslie Barron and Tarek Abdelrahman
9:05 : “Dynamic Constant Propagation for Compiled Languages” Tarun Prabhu and William Gropp
9:35 : “Model Free Adaptive Data Prefetching using Hypothesis Tests” Lionel Vincent , Stéphane Mancini , Suzanne Lesecq , Henri-Pierre Charles
10:30 Session 2
Panel Session: Thematic session about hardware support for dynamic compilation
In this panel session the organizers and the audience will share their ideas about dynamic compilation and hardware support for dynamic compilation, heterogeneity, optimization.
Question list to ignitiate discussion :
- What is the most useful HW support for HPC ? Complex instructions with parallelism, complex data movements, …
- Is JIT compilation suitable for HPC / IoT ?
- What is the best language compromise between performance and dynamic
- How to control power and energy at compilation level ?
Two previous workshop DCE (Dynamic Compilation Everywhere) and AMAS-DO (Architectural & Microarchitectural Support for Dynamic Optimization) has merged to create the 1st International Workshop on Dynamic Compilation for Architectural Heterogeneity and Program Optimization.
Call for paper
General purpose as well as integrated processors nowadays have to run programs written in a wide variety of languages with isolation concerns. Dynamic compilation, i.e. generate binary code at run- time, is becoming a viable solution for many usage scenarios, and one of the goals of this combined workshop is to present current research and look forward to what is going to happen in this field of growing interest for the coming years. Scientific challenges are multiple with many inter-relations: program representation (source code, intermediate representation, data sets), fast binary code generation, patches, hardware abstraction, garbage collection, performance observation, performance trade-offs, polymorphism, operating systems.
Furthermore, large-scale use of binary translation and on-the-fly code generation and optimization is becoming pervasive both as an enabler for virtualization, processor migration and also as processor implementation technology. The emergence and expected growth of just-in-time compilation, virtualization and Web 2.0 scripting languages brings to the forefront a need for efficient execution of this class of applications. The availability of multiple execution threads brings new challenges and opportunities, as existing binaries need to be transformed to benefit from multiple processors, and extra processing resources enable continuous optimizations and translation. The workshop scope includes support for decoding/translation, support for execution optimization and runtime support. It will set a high scientific standard for such experiments, and requires insightful analysis to justify all conclusions. The workshop will favor submissions that provide meaningful insights, and identify underlying root causes for the failure or success of the investigated technique. Acceptable work must thoroughly investigate and communicate why the proposed technique performs as the results indicate.
The main goal of this full-day workshop is to bring together researchers and practitioners with the aim of stimulating the exchange of ideas and experiences on the potential and limits of the underlying technology. The key focus is on the challenges and opportunities for such assistance and opening new avenues of research. A secondary goal is to enable dissemination of hitherto unpublished techniques from commercial projects.
Important new dates (anywhere on earth)
Paper : submission December 9, Author notification December 16 Final manuscript January 15
- Paper : submission December 23, Author notification January 6 Final manuscript January 15
Workshop: February 4, 2017
Submission & publication
Format: Full paper that consist of up to 6 pages, double column using electronic ACM format. http://www.acm.org/publications/proceedings-template
Publication: Accepted submissions will be published in the ACM Digital Library within its International Conference Proceedings Series (ICPS) with DOI publication number (ISBN number assigned to DCAHPO ’17 is 978-1-4503-4878-2)
• Erik ALTMAN, IBM, USA
• Mauricio BRETERNITZ, AMD, USA
• Henri-Pierre CHARLES, CEA, France
• Robert COHN, Intel, USA
• Bjoern FRANKE, Edinburgh Univ., UK
• Andreas KRALL, Wien TU, AT
• Vijay Janapa REDDI, Univ. of Texas at Austin, USA
• Youfeng WU, Intel, USA
Web site: https://dcahpo.wordpress.com/